Solid state semiconductor devices are conventionally fabricated on bulk monocrystalline silicon substrates and in monocrystalline silicon islands which are disposed on insulating substrates, commonly referred to as silicon-on-insulator (SOI) structures. SOI structures are particularly desirable when electrical isolation between silicon devices is important, such as in complementary symmetry metal oxide semiconductor (CMOS) field effect transistor (FET) applications. Sapphire (monocrystalline Al.sub.2 O.sub.3) is a commonly used substrate material for SOI structures and devices fabricated thereon are referred to as silicon-on-sapphire (SOS) devices.
In conventional SOS structures a plurality of monocrystalline silicon islands are disposed on a major surface of the sapphire substrate. It is desirable that the silicon islands be relatively thin, i.e. on the order of approximately 0.5 microns, so that when certain PN junctions are formed therein, by diffusion of dopants from the surface of the silicon, these junctions will extend for approximately the entire thickness of the silicon. This reduces the junction capacitance associated with the depletion region around the PN junction during device operation. However, there are several significant problems when using relatively thin epitaxial silicon on a sapphire substrate. A relatively high defect density, on the order of 10.sup.6 per centimeter occurs at the silicon/sapphire interface due to the nature of the epitaxial growth. Additionally, the silicon disposed within approximately 0.2 to 0.3 microns of the interface is oriented in a different crystallographic direction. Furthermore, silicon which is epitaxially deposited on sapphire substrates is typically characterized as having a relatively low carrier lifetime, e.g. on the order of approximately &lt;10 nanoseconds.
An alternative approach to forming SOI structures can be based on what is now referred to as the epitaxial lateral overgrowth (ELO) technique, disclosed in co-pending and commonly assigned U.S. patent application Ser. No. 608,544, METHOD FOR GROWING MONOCRYSTALLINE SILICON THROUGH A MASK LAYER, J. F. Corboy, Jr. et. al., filed May 10, 1984, now U.S. Pat. No. 4,578,142, issued Mar. 25, 1986. Basically, the ELO technique provides a means for forming high quality monocrystalline silicon over a mask layer of, for example, silicon dioxide. The monocrystalline silicon which is epitaxially deposited in the ELO process is of considerably better crystalline quality than the epitaxial silicon deposited on sapphire substrates. However, in the ELO process, depending upon the configuration of the insulator layer on which the monocrystalline silicon layer is formed, it may be necessary to form a layer which is thicker than 0.5 microns. Thus, in such a configuration, it becomes necessary to thin the monocrystalline silicon layer.
A variety of silicon thinning processes are conventionally used in the silicon processing art. However, none of the conventional thinning techniques has been found to be suitable in the present application. Plasma etching of a predetermined amount of the exposed monocrystalline silicon layer does not uniformly remove the silicon. Wet chemical etching also does not etch uniformly and is difficult to control reproducibly. A variety of other conventional silicon thinning techniques is also possible, although these other techniques typically add significant additional processing constraints and do not produce surfaces which are superior to the surface produced by the present invention. Examples of these other thinning techniques are processes which depend upon differing dopant concentrations so as to yield different etch rates, processes which depend upon particular crystallographic orientations, known as orientation dependent etches (ODEs), and electrochemical etching.
As further background to the subject invention, it should be noted that the process of thermally oxidizing silicon is well known in the semiconductor device fabrication art. It is known that oxidation rate is dependent upon such variables as ambient temperature, ambient pressure, ambient constituency and the time of exposure. For example, see KINETICS OF HIGH PRESSURE OXIDATION OF SILICON IN PYROGENIC STEAM, R. R. Razouk et al., Journal of Electrochemical Society, Solid State Science and Technology, Vol. 128, No. 10, October 1981, pp 2214-2220. As another example, the thermal oxidation of monocrystalline silicon is conventionally performed in what is referred to as local oxidation of silicon (LOCOS) processing, as described in ISOLATION TECHNOLOGY FOR SCALED MOS VLSI, W. G. Oldham, IEDM Technical Digest, 1982, pp 216-219. It is also known that the formation of an oxide on a silicon surface via an oxidation process consumes a certain quantity of the silicon at the surface. In conventional LOCOS processing the localized oxidation of silicon provides a field oxide which is part of the finished device and is located between devices for purposes of electrical isolation.